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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC145073/D Product Preview Dual 16-Bit Stereo Audio Sigma-Delta ADC CMOS The MC145073 is a dual-channel, 16-bit A/D converter intended for use in digital audio systems such as multimedia, DCC, DAT, and professional audio applications. It uses a sigma-delta architecture consisting of a second-order analog modulator and two stages of digital filtering for each channel. The analog modulator samples the input signal at 128 times the output data rate, performs a single-bit quantization, and shapes the quantization noise towards higher frequencies. Subsequent on-chip digital filters reject most of the shaped quantization noise and lower the data rate. Sixteen unique user-selectable interfacing modes make the MC145073 compatible with a multitude of application interfacing requirements. A single 5 V supply and a power-down mode reduce power supply requirements, making the part attractive for portable applications. * * * * * * * * * Single Supply, Operating Voltage Range: 4.5 to 5.5 V 128x OSR Sigma-Delta Modulator 82 dB Typical S/(N+D) Analog Inputs Can Be Driven as Either Differential or Single-Ended Clock Input May Be 128x, 256x, or 384x the Output Data Rate Out-of-Range Input Signals Internally Limited On-Chip Digital Filters: 5th Order Decimate-by-32 Comb Filter 121 Tap Decimate-by-4 FIR Filter User-Selectable Digital Filter Transition Bands Versatile Serial Digital Output Interface: Configurable as Master or Slave Data Can Be Either Left- or Right-Justified Interfaces to DSP56000/1 and TMS320TM DSPs I2S or Japanese Interface Compatibility CS5326 Compatible Interface Mode Multiplexing of Two MC145073s Accommodated Power-Down Mode Consumption: 2.0 mW Operating Temperature Range: - 40 to 85C AIN(+L) AIN(-L) MODULATOR COMB FILTER FIR FILTER 24 MC145073 1 DW SUFFIX SOG PACKAGE CASE 751E ORDERING INFORMATION MC145073DW SOG Package PIN ASSIGNMENT AIN(+L) AIN(-L) REF VDD(A) VSS(A) SUB VSS(D) VDD(D) FTP FTP SYNC SCLK 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 AIN(+R) AIN(-R) VAG CSEL0 CSEL1 FSEL ISYNC ISLAV IJUST IDOE CLK SDO * * CLK VOLTAGE REFERENCE MODES IN AIN(+R) AIN(-R) MODULATOR COMB FILTER FIR FILTER CLK DIVIDERS/DRIVER AND CONTROL LOGIC DIGITAL INTERFACE SERIAL INTERFACE This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. TMS320 is a trademark of Texas Instruments. REV 1 5/97 (c) Motorola, Inc. 1997 MOTOROLA MC145073 1 MAXIMUM RATINGS* (Voltages referenced to VSS, unless otherwise stated) Symbol VDD(A) VDD(D) Iin Vin(A) Vin(D) Tstg Tl Parameter Analog Supply Voltage Digital Supply Voltage DC Input Current, per Pin Analog Input Voltage Digital Inputs Storage Temperature Lead Temperature 1 mm From Case for 10 Seconds Value 6.0 6.0 20 VSS(A) - 0.3 to VDD(A) + 0.3 - 0.3 to VDD(D) + 0.3 - 65 to 150 260 Unit V V mA V V C C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Operation Ranges, Analog Specifications, AC Electrical Characteristics, and DC Electrical Characteristics tables. OPERATION RANGES Symbol VDD(A) VDD(D) Vin(A) fCLK CLOAD Ta Analog Supply Voltage Digital Supply Voltage Analog Input Voltage (AIN(+L), AIN(-L), AIN(+R), AIN(-R)) CLK Frequency Capacitive Load on Any Output Ambient Operating Temperature Parameter Min 4.5 4.5 -- 3.072 0 - 40 Max 5.5 5.5 1.9 18.432 50 85 Unit V V V p-p MHz pF C 1 2 Note NOTES: 1. Differential inputs greater than 3.8 V p-p will overload the modulators. These voltages are subject to the gain error tolerance specifications in the Analog Specifications table. 2. The internal clock frequency or input sampling frequency is governed by the divide mode and output data rate. The divide mode can be either 1, 2, or 3. The output data rate ranges from 24 kHz to 48 kHz. The minimum clock frequency of 3.072 MHz is for a 24 kHz output rate in the clock divide by 1 mode. The maximum clock frequency of 18.432 MHz is for a 48 kHz output rate in the clock divide by 3 mode. DC ELECTRICAL SPECIFICATIONS (Voltages referenced to VSS(D); Full Temperature and Voltage Ranges per Operation Ranges Table, unless otherwise indicated.) Symbol VIH VIL IIN VOH VOL IDDu(D) IDDd(D) IDDu(A) IDDd(A) PO Ppd Cin Parameter Minimum High-Level Digital Input Voltage Maximum Low-Level Digital Input Voltage Maximum Input Leakage Current Minimum High-Level Digital Output Voltage (IOH = - 20 A) Maximum Low-Level Digital Output Voltage (IOL = 20 A) Maximum Digital Power Supply Current, Operating Maximum Digital Power Supply Current, Power-Down Maximum Analog Power Supply Current, Operating Maximum Analog Power Supply Current, Power-Down Power Consumption, Operating Power Consumption, Power-Down Maximum Input Capacitance 4.4 0.1 45 250 10 150 250 2.0 20 Min 0.7 x VDD(D) 0.3 x VDD(D) 10 Max Unit V V A V V mA A mA A mW mW pF MC145073 2 MOTOROLA ANALOG SPECIFICATIONS (Full Temperature, CLK = 6.144 MHz in div1, VDD(A) = VDD(D) = 5.0 V, 1007.8 Hz Full-Scale Input Sinewave, 1.4 V p-p @ AIN(L) and AIN(R), Common Mode Input Voltage = 2.5 V. Measured bandwidth is 23 Hz to 24 kHz, inputs driven differentially per Figure 1.) Parameter Resolution Bits S/(N+D) Dynamic Range Total Harmonic Distortion (Vin = F.S.) Gain Error Gain Drift Channel to Channel Isolation PSRR (VDD(A)) PSRR (VDD(D)) Input Impedance Warm-Up Time (for Reference and Bias Circuits) Min 16 76 82 85 .003 5 50 90 60 100 40 1 Typ Max Unit Bits dB dB % % ppm/C dB dB dB k ms DIGITAL FILTER CHARACTERIZATION (Over full operating ranges per Operating Ranges table. Stated values are for input/output relationships from input of comb filter to output of FIR filter.) Output Data Rate Parameter P FSEL = low FIR Filter Passband Maximum Passband Ripple FIR Filter Transition Band FIR Filter Rejection (Min) Maximum Alias Level (Figure 3) Group Delay Setting Time FSEL = high FIR Filter Passband Maximum Passband Ripple FIR Filter Transition Band FIR Filter Rejection (Min) Maximum Alias Level (Figure 3) Group Delay Setting Time 0 to 14.5 0.1 14.5 to 18.2 - 84 - 86 33 49 0 to 20 0.1 20 to 25.0 - 84 - 86 33 49 0 to 21.7 0.1 21.7 to 27.3 - 84 - 86 33 49 kHz dB kHz dB dB Out CLKS Out CLKS 1, 2 3 3 0 to 13.3 0.1 13.3 to 17 - 84 - 86 33 49 0 to 18.3 0.1 18.3 to 23.5 - 84 - 86 33 49 0 to 20 0.1 20 to 25.8 - 84 - 86 33 49 kHz dB kHz dB dB Out CLKS Out CLKS 1, 2 3 3 32 kHz 44.1 kHz 48 kHz Unit Ui Notes N NOTES: 1. There is no rejection of input signals that are multiples of the sampling frequency (nxCLKI Filter Bandwidth, where n = 0, 1, 2, ...). 2. The maximum alias level spec does not apply to input signals in the range of 24 to 25.8 kHz in the 48 kHz output mode, 22.05 to 23.675 kHz in the 44.1 kHz output mode, or 16 to 17.2 kHz in the 32 kHz output mode. 3. One Out CLK (output clock) is equal in length to 128 internal CLKs or one SYNC clock period. MOTOROLA MC145073 3 VDD(A) VDD(A) 2 AIN(L) VDD(A) VDD(A) 2 AIN(R) VDD(A) 1 k 3 - + U2A 1 1 k 6 1 k 3 - + U1A 1 1 k 6 1 k AOUT(+L) RIN - U1B 7 AOUT(-L) 5+ AOUT(+R) RIN - U2B 7 AOUT(-R) 5+ 1 k Figure 1. Input Buffer-Driver NOTES: 1. Analog signals AIN(L) and AIN(R) are floating drivers. ROUT of source is to be equal to RIN of resistors. 2. U1, U2 -- MC33077. MC145073 4 MOTOROLA VDD(A) VDD(D) 47 F 0.1 F 1 F 33 *AIN(+L) 33 *AIN(-L) 33 *AIN(+R) 33 *AIN(-R) 1000 pF 23 AIN (-R) 1000 pF 24 AIN (+R) 1000 pF 2 AIN (-L) 1000 pF 1 AIN (+L) 4 5 VDD(A) VSS(A) 8 7 VDD(D) VSS(D) SCLK 12 SYNC 11 SDO 13 FSEL 19 AUDIO DATA PROCESSOR CSEL0 21 CSEL1 20 CONTROLLER MC74HCU04 CLK 14 IDOE ISLAV ISYNC IJUST 15 17 18 16 FTP 9 FTP 10 820 k 1 F 0.1 F 1 F 0.1 F 22 VAG 3 REF SUB 6 USER SELECTABLE DIGITAL STATES 22 pF 11.2896 MHz FOR 44.1 kHZ 22 pF Figure 2. MC145073 A/D Application Circuit * For best performance AIN(+L), AIN(-L) and AIN(+R), AIN(-R) should be differentially driven. AIN(+L) or AIN(+R) (and AIN(-L) or AIN(-R)) can be grounded for single ended configuration. Circuit in Figure 1 depicts input buffer circuit. MOTOROLA MC145073 5 0 CONVERTER GAIN (db) MAXIMUM ALIAS = - 86.713 db AT 24.0 kHz 0 CONVERTER GAIN (db) MAXIMUM ALIAS = - 87.5884 db AT 169.125 kHz - 86 - 86 0 24 48 96 120 144 168 192 216 240 264 288 INPUT FREQUENCY (kHz) OUTPUT DATA RATE = 48 kHz, FSEL = LOW 72 0 24 96 120 144 168 192 216 240 264 288 INPUT FREQUENCY (kHz) OUTPUT DATA RATE = 44.1 kHz, FSEL = HIGH 48 72 Figure 3. Digital Filter Response (Wideband) CLKI = 6.144 MHz DIGITAL FILTER RESPONSE (20 - 25.8 kHz TRANSITION BAND) 20 0 RESPONSE (dB AMPLITUDE) - 20 - 40 - 60 - 80 - 100 0 12 24 36 48 60 72 84 96 INPUT FREQUENCY (kHz) OUTPUT DATA RATE = 48 kHz, FSEL = HIGH DIGITAL FILTER RESPONSE (20 - 24 kHz TRANSITION BAND) 20 0 - 20 - 40 - 60 - 80 - 100 0 12 24 36 48 60 72 84 96 INPUT FREQUENCY (kHz) OUTPUT DATA RATE = 44.1 kHz, FSEL = HIGH RESPONSE (dB AMPLITUDE) Figure 4. Digital Filter Response (Narrowband) CLKI = 6.144 MHz SIMULATED DELAYS COMB FILTER INPUT COMB FILTER OUTPUT FIR FILTER OUTPUT COMB FILTER INPUT SIMULATED DELAYS COMB FILTER OUTPUT FIR FILTER OUTPUT 50 75 100 125 150 175 TIME (OUTPUT CLOCKS) 200 225 250 0 5 10 15 20 25 TIME (OUTPUT CLOCKS) 30 35 40 0 25 Figure 5. Group Delay and Setting Time MC145073 6 MOTOROLA AC ELECTRICAL SPECIFICATIONS (Full temperature and voltage ranges per Operation Ranges table. All timing parameters measured with respect to 30% and 70% of VDD(D) unless otherwise noted.) Figure 6 6 6 6 7 7 Symbol 1/tclk 1/tclki twch twcl tsync twsh Cin Parameter Master Clock (CLK) Frequency (Note 1) Internal Clock Frequency, CLKI (Note 1) tclki = 1/(fclk/Divide Ratio) Master Clock High, CLK Master Clock Low, CLK Sync Period (Master and Slave Modes) Sync High (Slave Mode) Input Capacitance (Except for Left/Right Channel Inputs) Master Mode: ISLAV = 0 8 8 8 tsclk twl/twh tCSY SCLK Period SCLK Duty Cycle Propagation Delay (Note 2) CLK Falling Edge to SYNC CLK Rising Edge to SYNC CLK Falling Edge to SYNC Propagation Delay (Note 2) CLK Falling Edge to SCLK CLK Rising Edge to SCLK CLK Falling Edge to SCLK Propagation Delay (Note 2) CLK Falling Edge to Serial Data Valid, SDO CLK Rising Edge to Serial Data Valid, SDO CLK Falling Edge to Serial Data Valid, SDO Slave Mode: ISLAV = 1 9 9 9 9 9 9 tsu th tsclkh tsclkl tsu th tCDV Setup Time (Note 3) SCLK to Rising Edge of CLK Hold Time (Note 3) SCLK to Rising Edge of CLK SCLK High SCLK Low Setup Time (Note 3) SYNC to Rising Edge of CLK Hold Time (Note 3) SYNC to Rising Edge of CLK Propagation Delay Clk Rising Edge to Serial Data Valid, SDO 1 2 3 twch tclk tclk + twch 20 20 15 0 15 0 ns ns ns ns ns ns 1 2 3 1 2 3 1 2 3 2 * tclki 0.667 2 * tclki 1.50 40 tclk + 40 2 * tclk + 40 40 tclk + 40 2 * tclk + 40 40 tclk + 40 2 * tclk + 40 ns ns ns ns ns ns ns ns ns ns 1 2, 3 1 2, 3 Divide Ratio Min 3.072 3.072 38 20 38 20 128 * tclki 20 128 * tclki 126 * tclki 20 Max 18.432 6.144 Unit MHz MHz ns ns ns ns pF 8 tCSC 8 tCDV twch + 40 2 * tclk + 40 3 * tclk + twch + 40 NOTES: 1. The internal clock frequency, or input sampling frequency (CLKI) is governed by the divide mode and output data rate. The divide mode can be either 1, 2, or 3. The output data rate ranges from 24 kHz to 48 kHz. The minimum clock frequency of 3.072 MHz corresponds to an output data rate of 24 kHz with the device in the clock divide by one mode. The maximum clock frequency of 18.432 MHz corresponds to an output data rate of 48 kHz with the device in the clock divide by three mode. 2. Propagation delay is measured with a capacitive load of 50 pF. 3. In the slave mode, SYNC or SCLK transitions can occur anywhere except 0 to - 5 ns relative to the CLK rising edge. MOTOROLA MC145073 7 twch CLK, CLKI SYNC twsh tclk, tclki twcl tsync Figure 6. Figure 7. CLK/1 CLK/2 CLK/3 tsclk twh SCLK twl SDO tCDV SYNC tCSY VALID DATA tCSC Figure 8. Serial Interface Timing (Master Mode: ISLAV = 0) CLK/1 CLK/2 CLK/3 tsclkh SCLK tsclkl SDO tCDV SYNC tsu, th VALID DATA tsu, th Figure 9. Serial Interface Timing (Slave Mode: ISLAV = 1) NOTE: CLK signals shown above represent the external clock at three different frequencies. MC145073 8 MOTOROLA PIN DESCRIPTIONS ANALOG PINS AIN(+L), AIN(-L) Left Channel Analog Inputs (Pins 1, 2) These two pins comprise the left channel analog differential inputs. The voltage range of signals applied to these pins is from V SS(A) to V DD(A). A positive full-scale input to the A/D is defined as a difference of 3.8 V p-p between A IN(+L) and A IN(-L). AIN(+R), AIN(-R) Right Channel Analog Inputs (Pins 24, 23) These two pins comprise the right channel analog differential inputs. The voltage range of signals applied to these pins is from V SS(A) to V DD(A). A positive full-scale input to the A/D is defined as a difference of 3.8 V p-p between A IN(+R) and A IN(-R). REF Output of the Internal Voltage Reference (Pin 3) The nominal value of this internal voltage reference is 2 V. The output of the reference is brought out to this pin to facilitate filtering. For proper device operation, this pin should be decoupled to V S S ( A ) with a 1.0 F electrolytic capacitor in parallel with a 0.1 F ceramic capacitor. In order to economize on filtering capacitors, the REF pin can be connected to VAG. However, this could result in a possible degradation of performance of the device at high signal levels. VAG Output of the Internal Analog Ground Generator (Pin 22) Analog ground is used to bias the internal analog circuits and is nominally 2 V. VAG is brought out to this pin to facilitate filtering. This pin should be decoupled to V SS(A) with a 1.0 F electrolytic capacitor in parallel with a 0.1 F ceramic capacitor for normal device operation. DIGITAL PINS CLK Master Clock Input (Pin14) This pin is the master clock input for the device. Analog input signals to the MC145073 are sampled at a rate equal to this clock frequency divided by 1, 2, or 3, depending on the state of clock mode pins CSEL1,0. The serial data output rate is equal to the input sample rate divided by 128. For example, if CLK is running at a 12.288 MHz rate, and divide by 2 is selected, then the output data rate is (12.288 MHz/2)/128 = 48 kHz. For more detail, see the Summary of Operating Modes section. SYNC Serial Interface Frame Sync Input/Output (Pin 11) The SYNC pin is an input or output depending on the state of the ISLAV pin. The SYNC signal resets and synchronizes the serial interface transmitter and receivers, as well as most internal clocks. Left channel serial output data is transmitted when the SYNC signal is active high, and right channel data is transmitted when the SYNC signal is low. See the Serial Interface Description section for more information. SCLK Serial Interface Clock Input/Output (Pin 12) The SCLK pin is an input or output depending on the state of the I SLAV pin. Serial output data is clocked out of the MC145073 on the rising edge of SCLK. When SCLK is an input, it is reclocked by the internal sample rate clock, CLKI, before being used by the MC145073 to clock out the serial data. This reclocking ensures that rapid current changes through the SDO pin do not affect the analog performance of the device. See the Serial Interface Description section for more information. SDO Serial Interface Data Output (Pin 13) The A/D conversion results for the left and right channels are output on this pin. Data is shifted out of the MC145073 MSB first, with the left channel data preceding the right channel data. The serial output data is clocked out on the rising edge of SCLK. See the Serial Interface Description section for more information. FTP Factory Test Mode Inputs (Pins 9, 10) These pins should be connected to VSS(A) for normal device operation. CSEL0, CSEL1 Clock Divide Mode Select Inputs (Pins 21, 20) The device master clock input is divided by 1, 2, or 3, or the device is placed in a power-down mode depending on the state of these pins. See the Summary of Operating Modes section for more information. FSEL FIR Filter Response Select Input (Pin 19) A low level on the FSEL input selects a FIR filter transition band from 20 to 25.8 kHz at the 48 kHz output data rate. A high level on the FSEL pin selects a filter transition band from 20 to 24 kHz at the 44.1 kHz output data rate. See the Summary of Operating Modes section for more information. ISYNC Serial Interface Sync Format Select Input (Pin 18) A low level input on the ISYNC pin selects a SYNC rising edge one SCLK cycle before the initiation of a serial data transfer. A high level on the ISYNC pin will select a SYNC rising edge that is coincident with the initiation of a serial data transfer. See the Summary of Operating Modes and the Serial Interface Description sections for more information. ISLAV Serial Interface Slave Mode Select Input (Pin 17) This pin controls the direction of the serial interface SYNC and SCLK signals. A low level on the ISLAV pin will configure the SYNC and SCLK pins as outputs, while a high level on the ISLAV pin will configure the SYNC and SCLK pins as inputs. See the Summary of Operating Modes and the Serial Interface Description sections for more information. MOTOROLA MC145073 9 IJUST Serial Interface Data Justification Select Input (Pin 16) A low level on the IJUST pin will cause the serial output data to be left justified relative to the SYNC signal. A high level on the IJUST pin will select right justification of the serial output data. See the Summary of Operating Modes and the Serial Interface Description sections for more information. IDOE Serial Interface Data Output Enable (Pin 15) This pin controls the state of the SDO pin between 16-bit data word transfers. A high level on this pin will force the SDO pin to a low level between serial data words, while a low level on the I DOE pin will force the SDO pin to a high-impedance state between data words. See the Summary of Operating Modes and the Serial Interface Description sections for more information. POWER SUPPLY PINS VDD(A) (Pin 4) Positive analog power supply input. The voltage range for this pin is 4.5 to 5.5 V with respect to V SS(A). The absolute value of the difference between V DD(A) and V DD(D) must not exceed 0.5 V. For proper device operation, this pin should be decoupled to V SS(A) with a 1.0 F or larger capacitor. VSS(A) (Pin 5) Negative analog power supply input. This pin should be connected to ground for normal device operation. VDD(D) (Pin 8) Positive digital power supply input. The voltage range for this pin is 4.5 to 5.5 V with respect to V SS(D). The absolute value of the difference between V DD(A) and V DD(D) must not exceed 0.5 V. For proper device operation, this pin should be decoupled to V SS(D) with a 1.0 F or larger capacitor. VSS(D) (Pin 7) Negative digital power supply input. This pin should be connected to ground for normal device operation. SUB (Pin 6) Substrate connection. This pin should be connected to V SS(A) for normal device operation. FUNCTIONAL DESCRIPTION The MC145073 is a 16-bit stereo audio A/D converter intended for use in digital audio systems. The MC145073 uses a sigma-delta architecture consisting of a second order analog modulator followed by two stages of digital filtering for each channel. The analog modulator samples the input signal at a very high rate (128x the output data rate), performs a single bit quantization, and shapes the quantization noise towards out-of-band frequencies. The digital filters of the MC145073 reject most of the shaped quantization noise, and lower the serial data output rate. The digital filtering is implemented with a 5th order, decimate-by-32 comb filter followed by a 121 tap, decimate-by-4, FIR filter on each channel. In addition to rejecting quantization noise, the FIR filter cancels the curvature in the response of the preceding comb filter. The comb and FIR filters also provide anti-alias filtering of out-of-band signals present at the input to the device. The analog inputs to the MC145073 can be fully differential (both inputs dynamic and 180 degrees out of phase), or single-ended (positive inputs dynamic while negative inputs are static at a level in the middle of the supply range). Analog input signals that exceed the differential analog input voltage range of 3.8 V p-p are clipped in order to prevent overflow of the digital filters. The MC145073 operates from a single 5 V power supply. For portable or other low power applications, a power-down mode is available. The operation of the MC145073 can be tailored to specific applications by proper selection of the states of seven mode select pins. These mode pins control the divide ratio of the master clock, the FIR filter response, and the serial interface format. The master clock input can be divided by either 1, 2, or 3 to yield the input sampling rate. This means that the input clock frequency is either 128x, 256x, or 512x the serial output data rate. NOTE The oversampling ratio (OSR), which is the ratio of input sampling frequency to output data rate, is 128x in all three cases. Two sets of FIR filter coefficients are stored in the on- board ROM of the MC145073. One set provides a transition band from 20 kHz to 25.8 kHz for operation at the 48 kHz output data rate. The other set of FIR filter coefficients provides a transition band from 20 kHz to 25 kHz for use with the 44.1 kHz output data rate. Four mode select pins configure the serial interface. This yields sixteen possible serial interface operating modes. Included are modes that provide for interfacing directly to Motorola and TI general purpose DSPs, multiplexing of two MC145073s, as well as formats similar to the CS5326 interface. MC145073 10 MOTOROLA SUMMARY OF DEVICE OPERATING MODES The seven pins summarized in the tables below configure the MC145073 to operate in one of the modes specified. The modes can be chosen in any combination. CSEL1 0 0 1 1 CSEL0 0 1 0 1 Master CLK Divider Select Power-Down Divide CLK by 1 Divide CLK by 2 Divide CLK by 3 FSEL 0 1 FIR Filter Transition Band Select 20 kHz - 25.8 kHz Transistion Band 6.144 MHz Input Rate, 48 kHz Output Data Rate. 20 kHz - 25 kHz Transistion Band 5.6448 MHz Input Rate, 44.1 kHz Output Data Rate serial interface is provided in the AC Electrical Specifications section . Compatibility with the DSP56000/1 and TMS320 general- purpose DSPs is accomplished by applying the appropriate logic level to the I SYNC pin. The phase of the rising edge of the SYNC signal is different for the DSP56000 and TMS320 applications, while the falling edge of SYNC is not critical in such applications. To interface to one or two MC145073s, the DSP56000/56001 should be configured as follows: network mode, four time slots per frame, 16 bits per slot, continuous clock, and control signals configured as either a master or slave. If interfacing to a TMS320 is desired, the serial interface should be configured in continuous mode without frame sync. NOTE The TMS320 interface must be initialized with frame sync enabled, and then switched to the no frame sync mode after initialization. The I JUST and I DOE serial interface mode control inputs are provided to facilitate multiplexing of two MC145073s. The I JUST input selects between left and right justification of the serial output data relative to the SYNC signal, while the I DOE input provides a way to force the SDO pin to the high impedance state between the output data words. To multiplex the serial data outputs of two MC145073s onto the same SDO line, I D O E must be forced low on both MC145073s, while the I JUST pin is forced high on one MC145073 and low on the other. The MC145073s must be in the slave mode (I SLAV=1) when multiplexing. It is not possible to operate with one MC145073 as a master tied to a second MC145073 operating as a slave due to the reclocking of the SYNC and SCLK inputs in the slave mode (see Operation with the MC145073 as a Slave (I SLAV = 1) section). NOTE When multiplexing two MC145073 devices, all four analog channels are sampled at exactly the same phase. In Figures 10 and 11, the internal clock signal CLKI is plotted instead of CLK. This is due to the fact that all internal clocks, as well as the serial interface, are slaved to this divided version of the master clock. Input signals to the serial interface are reclocked by CLKI to reduce the amount of noise injected into the analog section of the MC145073. Serial output data and high-impedance states of the SDO pin are clocked out relative to CLKI. This reclocking can cause a shift in phase of SDO relative to SCLK when operating in the slave mode. In cases where the MC145073 output is multiplexed with another device, the clock divide by 1 mode is recommended. NOTE If the clock divide by 2 or 3 mode is selected, it is impossible to know the exact phase of CLKI. On initial power-up or recovery from a power-down condition, the first 68 serial output words of the MC145073 are indeterminate. This is because the digital filters and internal logic of the MC145073 must settle. This time is also used to charge the external REF filter capacitor. ISYNC 0 Serial Interface SYNC Signal Format SYNC rising edge is one SCLK cycle before the start of the serial output data transfer. (This is compatible with the DSP5600/56001 and TMS320 interface definitions.) SYNC rising edge is coincident with the start of the serial output data transfer. (This is compatible with the CS5326 interface definition.) 1 ISLAV 0 1 Serial Interface Master or Slave Select MC145073 is a master, SYNC and SCLK are outputs. MC145073 is a slave, SYNC and SCLK are inputs (re-clocked by the MC145073 internal clock, CLKI). IJUST 0 1 Serial Interface Data Justification Select Serial output data is left justified relative to the SYNC signal. Serial output data is right justified relative to the SYNC signal. IDOE 0 1 Serial Interface Data Output Enable SDO goes to a high-impedance state between 16-bit output words. SDO is forced low between 16-bit output words. SERIAL INTERFACE DESCRIPTION As summarized in the previous section, the format of the serial interface is controlled by four mode pins: I SYNC , I SLAV, I JUST, and I DOE. These control inputs can be configured in any combination, yielding 24 = 16 unique modes. The following two subsections describe the format of the serial interface for these various modes. Timing information for the MOTOROLA MC145073 11 Operation with the MC145073 as a Master (ISLAV = 0) When ISLAV = 0, the SYNC and SCLK signals are defined as outputs, and the MC145073 is configured as master device. In this mode there are eight possible serial formats as illustrated in Figure 10. The phase of the SYNC output can precede the serial output data by one SCLK cycle (compatible with DSP56000/56001, TMS320, and I2S interface format), or the SYNC signal can be coincident with the serial output data (similar to the CS5326 serial interface format). As shown in Figure 10, with each of these two SYNC formats there are four possible formats for the serial output data. Serial output data is shifted out MSB first, with left channel data preceding the right channel data. All of the serial interface outputs, SYNC, SCLK, and SDO are initiated by a CLKI rising edge. There are 128 CLKI cycles, and 64 SCLK cycles per output data cycle. Multiplexing of two MC145073s is not feasible in the master mode since the exact phase of the output cannot be controlled. NOTE The serial data in one output cycle represents data that was simultaneously sampled on the two analog input channels. It is possible to initiate the device in the slave mode described in the Operation with the MC145073 as a Slave (I SLAV = 1) section, and then switch to master mode. Once set, the phase of SYNC should not change. Operation with the MC145073 as a Slave (ISLAV = 1) When ISLAV = 1 the SYNC and SCLK signals are defined as inputs, and the MC145073 is configured as a slave device. However, the slave mode of the MC145073 is not a true slave mode since the SYNC and SCLK inputs are reclocked by the internal sample clock, CLKI. These internal reclocked versions of SYNC and SCLK are shown in Figure 11, in addition to the external SYNC and SCLK signals. Similar to the master mode of the previous section, there are two formats for the SYNC signal, and four SDO formats, yielding eight possible slave modes. Multiplexing of two MC145073s in the slave mode is performed by forcing IDOE low on both MC145073s, and forcing I JUST high on one MC145073 and low on the other. NOTE When multiplexing two MC145073s, the master clock divide by 1 mode should be used (CSEL1,0 = 0,1) so that the exact phase of CLKI is determined. MC145073 12 MOTOROLA IJUST = 0 IJUST = 1 MOTOROLA 128 CLKI CYCLES 64 SCLK CYCLES SAMPLE n D15L D14L D13L D1L D0L 16 HIGH Z STATES D15R SAMPLE n D14R D13R D1R SAMPLE n D0L 16 0's D15R D14R D0R 16 0's D13R D1R D0R 16 HIGH Z STATES SAMPLE n + 1 D15L D14L SAMPLE n D15L D14L D13L D1L SAMPLE n + 1 D15L D14L SAMPLE n 16 HIGH Z STATES D1R D0R D15L D14L D13L D1L D0L 16 HIGH Z STATES D15R D14R D0R D13R D1R SAMPLE n SAMPLE n 16 0's D15L D14L D13L D1L D0L 16 0's D13R D1R SAMPLE n D15L D14L D0R D1R D0R CLKI SCLK SYNC (ISYNC = 0) SYNC (ISYNC = 1) SDO (IDOE = 0) SDO (IDOE = 1) SAMPLE n - 1 SDO (IDOE = 0) SAMPLE n - 1 Figure 10. Serial Interface Operation with MC145073 Configured as Master (ISLAV = 0) SDO (IDOE = 1) MC145073 13 ISYNC = 0 ISYNC = 1 IJUST = 0 IJUST = 1 MC145073 14 128 CLKI CYCLES 64 SCLK CYCLES SAMPLE n D15L SAMPLE n D15L D14L D13L D1L D0L 16 0's SAMPLE n 16 HIGH Z STATES D15L D14L D13L D1L SAMPLE n 16 0's D15L D14L D13L D1L D0L 16 0's D0L 16 HIGH Z STATES D14L D13L D1L D0L 16 HIGH Z STATES SAMPLE n D15R D14R SAMPLE n D15R D14R D13R D1R D0R 16 0's D13R D1R SAMPLE n D15R D14R D13R D1R SAMPLE n D15R D14R D0R D0R D13R D1R D0R 16 HIGH Z STATES D14L D13L D14L D13L D1R D0R D1R D0R CLKI EXTERNAL SCLK INTERNAL SCLK EXTERNAL SYNC INTERNAL SYNC EXTERNAL SYNC INTERNAL SYNC SAMPLE n + 1 SDO (IDOE = 0) SAMPLE n + 1 SDO (IDOE = 1) SAMPLE n - 1 Figure 11. Serial Interface Operation with MC145073 Configured as Slave (ISLAV = 1) SDO (IDOE = 0) SAMPLE n - 1 MOTOROLA SDO (IDOE = 1) PACKAGE DIMENSIONS DW SUFFIX SOG PACKAGE CASE 751E-04 -ANOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.60 7.40 2.65 2.35 0.49 0.35 0.90 0.41 1.27 BSC 0.32 0.23 0.29 0.13 8 0 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0 8 0.395 0.415 0.010 0.029 24 13 -B- P 12 PL 0.010 (0.25) M B M 1 12 D 24 PL J M 0.010 (0.25) TA S B S F R X 45 C -TSEATING PLANE G 22 PL K M MOTOROLA MC145073 15 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 INTERNET: http://motorola.com/sps MC145073 16 MC145073/D MOTOROLA |
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